The present invention relates to a technique which may be suitably adapted to a semiconductor storage device and particularly to a semiconductor storage device including a DRAM (Dynamic Random Access Memory).
The DRAM following a 16K-generation device utilizing one-transistor/one-capacitor cell (hereinafter, abbreviated as 1T cell) introduces a low noise construction in which a pair-line is formed of bit lines connecting the identical numbers of memory cells and this pair-line is connected with sense amplifiers. Thereby, a low level signal appearing on one of the bit-line pair from the selected memory cells is discriminated stably. Namely, in a system called a differential sense system, only a difference voltage between the lines forming a pair is amplified, the identical voltage is canceled and only a signal is amplified in the sense amplifier.
Discrimination of binary information in the differential sense system is carried out through discrimination of polarity in which a reference is made to a voltage on one line of the bit line pair for comparison but this discrimination characteristic is closely related to a positional relationship of the bit line pair for the sense amplifier and therefore various bit-line arrangement methods have been proposed. As a typical bit-line arrangement method which has been used practically in the DRAM of 1T cell, an open bit-line arrangement and a fold-back bit-line arrangement have been proposed.
FIG. 17 shows an open bit-line arrangement constitution method in which an entire part is formed of two sets of cell array because one bit line is divided into two sections and these sections are used as a pair-line (formed of first bit line BL and second bit line /BL). In this open bit-line arrangement, memory cells are arranged at all intersections of the word line and bit line and thereby an area of the memory array can be relatively reduced. Therefore, this constitution method is suitable to obtain a chip of small area. For example, when the minimum design size is defined as F, the cell area can be set to 4F2.
However, since the bit-line pair exists on different cell arrays, noise generated on one cell array appears on only one of the bit-line pair, resulting in a demerit that the cell array is weak for noise. Moreover, since the sense amplifiers must be arranged at the central area of the bit-line while the electric characteristic of the bit-line pair is balanced, here rises a problem that there is no flexibility in the layout of the sense amplifiers.
FIG. 18 shows a fold-back bit-line arrangement construction method in which a bit-line pair is constructed within one cell array. In this fold-back bit-line arrangement, noise generated in one cell array appears on both lines of the bit-line pair, resulting in a merit that the cell array is superior in the noise resistance characteristic. Moreover, since the sense amplifier arrangement has reasonable flexibility, the layout design of sense amplifiers can be realized comparatively easier than the open bit-line arrangement.
However, since the memory cells can be arranged only a half of the intersections between the word line and bit line, here rises a problem that an area of memory array relatively increases and thereby the chip size becomes large. When the minimum design size is defined as F, the cell area can be expressed as 8F2 and the memory cell area becomes twice the area in the open bit-line arrangement.
As explained above, the open bit-line arrangement assures small memory array but is weak in noise, while the fold-back bit-line arrangement is superior in noise but cannot provide a small memory array. Accordingly, the fold-back bit-line arrangement having excellent noise resistance characteristic has been employed to the devices up to the 64K to 64 Mbit generations but for the devices after the 64 Mbit generations, reduction of cell area through improvement of circuit technology such as new bit line arrangement method and multi-division method is now investigated in addition to improvement of memory cell construction and progress of the scale-down processing technique.
For example, the official gazettes of the Japanese Unexamined Patent Application Publications No. Hei 7(1995)-94597 and No. Hei 7(1995)-254650 disclose the fold-back bit-line arrangement in which the bit lines are formed in two layers resulting in the cell area of 4F2 in order to realize reduction of noise and high density integration of memory cells. In this construction method, the memory cells are connected in the lower wiring side and a pair of the upper layer and lower layer wirings form the bit-line pair in order to form a fold-back bit-line arrangement. Moreover, for the purpose of lowering coupling noise between the bit lines, the connection change-over points are provided in a constant interval on the upper layer and lower layer wirings and the upper layer wiring and lower layer wiring are crossed at these change-over points.
However, the investigation by the inventors of the present invention has made it apparent that noise generated between bit lines easily appears on the memory cells and thereby problems such as destruction of cell information and drop of an S/N ratio of memory cells are generated because all memory cells are connected to the lower layer wiring forming one of the bit-line pair in the fold-back bit-line arrangement in which the bit lines are formed in two layers.
Moreover, since a crossing portion in which the third layer wiring is added is necessary to realize the three-dimensional crossing construction of the upper layer wiring and lower layer wiring, the number of the memory cells can be arranged which is twice compared with the existing fold-back bit-line arrangement, but a problem that efficiency of area reduction is deteriorated is still left unsolved.
Therefore, an object of the present invention is to provide the technique to realize a DRAM in which a cell area having reduced influence of the bit-line noise on the memory cells is defined to 4F2.
The above-mentioned and other objects and features will become apparent from the description of this specification and the accompanying drawings.
The typical invention among those disclosed in this specification will be briefly explained below.
The present invention comprises a plurality of bit-line pairs of the fold-back arrangement connected to sense amplifiers, a plurality of first word lines formed of the first wiring arranged in the direction crossing a plurality of bit-line pairs and a plurality of second words lines formed of the second wiring with these first word lines and second word lines arranged in parallel with the same pitch, wherein the first word lines and the second word lines are alternately arranged with the interval identical to xc2xd of the pitch in the horizontal direction, the memory cells are arranged at the intersections of the first word lines and one of the bit-line pair and the intersections of the second word lines and the other of the bit-line pair. The memory cell is formed of a semiconductor substrate in which a channel region is formed on the main surface thereof, a gate electrode arranged integrally via a gate insulation film in both sides in the row direction of the substrate and is always maintained at the voltage identical to that of the substrate, a bit line which is connected to the upper side of the substrate and extended in the column direction to form one or the other side of the bit-line pair and an accumulation node of a capacitor which is connected to the lower side of the substrate and is provided within a groove formed on the semiconductor substrate. A conductive film of the same layer as the gate electrode is arranged on the bit line via the insulation film, and both side surfaces in the row direction and upper surface of the bit line are shielded with a conductive film.